Adders are widely used in ASICs and represent one of the most common and basic circuit functions of general purpose digital computers and processors. Adder based circuits include adders, subtractors, adder-subtractors, incrementors, decrementors, incrementor-decrementors, and absolute value calculators, to name a few. Nearly every datapath module of nearly every digital IC includes adder based circuits. Thus, adders are crucial to the operation of computers, processors and controllers.
Each element on a chip, be it an element of an adder or some other device, is derived from a library of cells, the library being technology dependent based on the processing technology used to fabricate the IC chip. Each cell requires some space (area) on the chip, and the cells forming the element require some depth to the chip. Consequently, the elements formed by the cells require some minimum amount of volume on the chip.
Most adders are implemented to perform a Boolean function such that S_n=A_n+B_n, where S_n is the digital output and A_n and B_n are the digital inputs. Most adders are composed of AND, OR and Exclusive-NOR (XNOR) elements. However, these elements often require considerable space and depth, and signal propagation through the element may cause timing delays.
As integrated circuit processing continues to advance, the need increases for smaller, faster adders. The present invention is directed to this need.
The aforementioned application of Gashkov et al. describes a comparator architecture for ICs based on a Fibonacci series. The resulting circuit is smaller and has less depth, and hence less delay, than a corresponding comparator of traditional design. The present invention extends that concept to adders for ICs.